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> // Revision 1.18  2001/11/08 14:54:23  mohor
> // Comments in Slovene language deleted, few small fixes for better work of
> // old tools. IRQs need to be fix.
> //
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< reg 										threi_clear; // THRE interrupt clear flag
---
> //reg 										threi_clear; // THRE interrupt clear flag
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> /*
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< 		threi_clear <= #1 1; // reset bits in Modem Status Register
---
> 		threi_clear <= #1 1;
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> */
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< 	lsr1r <= #1 wb_rst_i ? 0 : // clear status on read
< 				lsr_mask ? 0 : lsr1 && ~lsr1_d; // set on rise
---
> 	if (wb_rst_i) lsr1_d <= #1 0;
> 	else	lsr1r <= #1	lsr_mask ? 0 : lsr1 && ~lsr1_d; // set on rise
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< 	lsr2r <= #1 wb_rst_i ? 0 : // clear status on read
< 				lsr_mask ? 0 : lsr2 && ~lsr2_d; // set on rise
---
> 	if (wb_rst_i) lsr2_d <= #1 0;
> 	else lsr2r <= #1 lsr_mask ? 0 : lsr2 && ~lsr2_d; // set on rise
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< 	lsr3r <= #1 wb_rst_i ? 0 : // clear status on read
< 				lsr_mask ? 0 : lsr3 && ~lsr3_d; // set on rise
---
> 	if (wb_rst_i) lsr3_d <= #1 0;
> 	else lsr3r <= #1 lsr_mask ? 0 : lsr3 && ~lsr3_d; // set on rise
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< 	lsr4r <= #1  wb_rst_i ? 0 :
< 			  lsr_mask ? 0 : lsr4 && ~lsr4_d;
< 
---
> 	if (wb_rst_i) lsr4_d <= #1 0;
> 	else lsr4r <= #1 lsr_mask ? 0 : lsr4 && ~lsr4_d;
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< 	lsr5r <= #1 wb_rst_i ? 1 :
< 			(lsr_mask || iir_read || tx_fifo_write) ? 0 :  lsr5 && ~lsr5_d;
---
> 	if (wb_rst_i) lsr5_d <= #1 0;
> 	else lsr5r <= #1 (lsr_mask || iir_read || tx_fifo_write) ? 0 :  lsr5 && ~lsr5_d;
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< 	lsr6r <= #1 wb_rst_i ? 1 :
< 				 (lsr_mask || tx_fifo_write) ? 0 : lsr6 && ~lsr6_d;
---
> 	if (wb_rst_i) lsr6_d <= #1 0;
> 	else lsr6r <= #1 (lsr_mask || tx_fifo_write) ? 0 : lsr6 && ~lsr6_d;
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< 	lsr7r <= #1  wb_rst_i ? 0 :
< 			  lsr_mask ? 0 : lsr7 && ~lsr7_d;
---
> 	if (wb_rst_i) lsr7_d <= #1 0;
> 	else lsr7r <= #1 lsr_mask ? 0 : lsr7 && ~lsr7_d;
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< assign thre_int = threi_clear ? 0 : ier[`UART_IE_THRE] && lsr[`UART_LS_TFE];
---
> //assign thre_int = threi_clear ? 0 : ier[`UART_IE_THRE] && lsr[`UART_LS_TFE];
> assign thre_int = ier[`UART_IE_THRE] && lsr[`UART_LS_TFE];
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< 		iir[`UART_II_II] <= #1 1'b0;
---
> 		iir[`UART_II_II] <= #1 0;