1,62d0 < ////////////////////////////////////////////////////////////////////// < //// //// < //// uart_debug_if.v //// < //// //// < //// //// < //// This file is part of the "UART 16550 compatible" project //// < //// http://www.opencores.org/cores/uart16550/ //// < //// //// < //// Documentation related to this project: //// < //// - http://www.opencores.org/cores/uart16550/ //// < //// //// < //// Projects compatibility: //// < //// - WISHBONE //// < //// RS232 Protocol //// < //// 16550D uart (mostly supported) //// < //// //// < //// Overview (main Features): //// < //// UART core debug interface. //// < //// //// < //// Author(s): //// < //// - gorban@opencores.org //// < //// - Jacob Gorban //// < //// //// < //// Created: 2001/12/02 //// < //// (See log for the revision history) //// < //// //// < ////////////////////////////////////////////////////////////////////// < //// //// < //// Copyright (C) 2000, 2001 Authors //// < //// //// < //// This source file may be used and distributed without //// < //// restriction provided that this copyright statement is not //// < //// removed from the file and that any derivative work contains //// < //// the original copyright notice and the associated disclaimer. //// < //// //// < //// This source file is free software; you can redistribute it //// < //// and/or modify it under the terms of the GNU Lesser General //// < //// Public License as published by the Free Software Foundation; //// < //// either version 2.1 of the License, or (at your option) any //// < //// later version. //// < //// //// < //// This source is distributed in the hope that it will be //// < //// useful, but WITHOUT ANY WARRANTY; without even the implied //// < //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// < //// PURPOSE. See the GNU Lesser General Public License for more //// < //// details. //// < //// //// < //// You should have received a copy of the GNU Lesser General //// < //// Public License along with this source; if not, download it //// < //// from http://www.opencores.org/lgpl.shtml //// < //// //// < ////////////////////////////////////////////////////////////////////// < // < // CVS Revision History < // < // $Log: not supported by cvs2svn $ < // Revision 1.2 2001/12/12 22:17:30 gorban < // some synthesis bugs fixed < // < // Revision 1.1 2001/12/04 21:14:16 gorban < // committed the debug interface file < // 63a2,67 > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > 64,64d1 < // synopsys translate_off 66,66d68 < // synopsys translate_on 68,68d69 < `include "uart_defines.v" 69a71,72 > > 70,70c73,73 < module uart_debug_if (/*AUTOARG*/ --- > module uart_debug_if ( 70a74,74 > 71,71d73 < // Outputs 72a76,76 > 73,73d75 < // Inputs 81a85,85 > input [1:0] fcr; 82,82d84 < input [1:0] fcr; /// bits 7 and 6 of fcr. Other bits are ignored 96,96c99,99 < always @(/*AUTOSENSE*/fcr or ier or iir or lcr or lsr or mcr or msr --- > always @(fcr or ier or iir or lcr or lsr or mcr or msr 98a102,102 > 99,99d101 < // 8 + 8 + 4 + 4 + 8 100a104,104 > 101,101d103 < // 5 + 2 + 5 + 4 + 5 + 3 103a107,107 > endcase 104,104d106 < endcase // case(wb_adr_i) 105a109,109 > endmodule 106,106d108 < endmodule // uart_debug_if