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> // Revision 1.18  2001/12/03 21:44:29  gorban
> // Updated specification documentation.
> // Added full 32-bit data bus interface, now as default.
> // Address is 5-bit wide in 32-bit data bus mode.
> // Added wb_sel_i input to the core. It's used in the 32-bit mode.
> // Added debug interface with two 32-bit read-only registers in 32-bit mode.
> // Bits 5 and 6 of LSR are now only cleared on TX FIFO write.
> // My small test bench is modified to work with 32-bit mode.
> //
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< 	counter_t, rf_count, rf_data_out, rf_error_bit, rf_overrun, rx_reset, lsr_mask, rstate);
---
> 	counter_t, rf_count, rf_data_out, rf_error_bit, rf_overrun, rx_reset, lsr_mask, rstate, rf_push);
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> output 				rf_push;