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> // Revision 1.23  2001/11/12 21:57:29  gorban
> // fixed more typo bugs
> //
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< wire [7:0] 								counter_b;
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< 	counter_t, counter_b, rf_count, rf_data_out, rf_error_bit, rf_overrun, rx_reset, lsr_mask);
---
> 	counter_t, rf_count, rf_data_out, rf_error_bit, rf_overrun, rx_reset, lsr_mask);
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< 			wb_dat_o <= #1 rf_data_out[9:2];
---
> 			wb_dat_o <= #1 rf_data_out[10:3];
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< wire	thre_write;
---
> wire	fifo_write;
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< assign thre_write = (wb_we_i && wb_addr_i == `UART_REG_TR && !dlab);
---
> assign fifo_write = (wb_we_i && wb_addr_i == `UART_REG_TR && !dlab);
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< assign lsr0 = (rf_count!=4'b0);  // data in receiver fifo available
---
> assign lsr0 = (rf_count==0 && fifo_write);  // data in receiver fifo available set condition
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> assign lsr4 = rf_data_out[2]; // break error in the character
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< assign lsr4 = (counter_b==8'b0); // break counter reached 0
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> reg 	 lsr0_d;
> 
> always @(posedge clk or posedge wb_rst_i)
> 	if (wb_rst_i) lsr0_d <= #1 0;
> 	else lsr0_d <= #1 lsr0;
> 
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> 	else lsr0r <= #1 (rf_count==1 && fifo_read) ? 0 : // deassert condition
> 					  lsr0r || (lsr0 && ~lsr0_d); // set on rise of lsr0 and keep asserted until deasserted 
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< 	else lsr0r <= #1 lsr0;
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< 	else	lsr1r <= #1	lsr_mask ? 0 : lsr1 && ~lsr1_d; // set on rise
---
> 	else	lsr1r <= #1	lsr_mask ? 0 : lsr1r || (lsr1 && ~lsr1_d); // set on rise
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< 	else lsr2r <= #1 lsr_mask ? 0 : lsr2 && ~lsr2_d; // set on rise
---
> 	else lsr2r <= #1 lsr_mask ? 0 : lsr2r || (lsr2 && ~lsr2_d); // set on rise
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< 	else lsr3r <= #1 lsr_mask ? 0 : lsr3 && ~lsr3_d; // set on rise
---
> 	else lsr3r <= #1 lsr_mask ? 0 : lsr3r || (lsr3 && ~lsr3_d); // set on rise
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< 	else lsr4r <= #1 lsr_mask ? 0 : lsr4 && ~lsr4_d;
---
> 	else lsr4r <= #1 lsr_mask ? 0 : lsr4r || (lsr4 && ~lsr4_d);
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< 	if (wb_rst_i) lsr5_d <= #1 0;
---
> 	if (wb_rst_i) lsr5_d <= #1 1;
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< 	if (wb_rst_i) lsr5r <= #1 0;
---
> 	if (wb_rst_i) lsr5r <= #1 1;
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< 	else lsr5r <= #1 (lsr_mask || iir_read || tx_fifo_write) ? 0 :  lsr5 && ~lsr5_d;
---
> 	else lsr5r <= #1 (lsr_mask || iir_read || tx_fifo_write) ? 0 :  lsr5r || (lsr5 && ~lsr5_d);
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< 	if (wb_rst_i) lsr6_d <= #1 0;
---
> 	if (wb_rst_i) lsr6_d <= #1 1;
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< 	if (wb_rst_i) lsr6r <= #1 0;
---
> 	if (wb_rst_i) lsr6r <= #1 1;
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< 	else lsr6r <= #1 (lsr_mask || tx_fifo_write) ? 0 : lsr6 && ~lsr6_d;
---
> 	else lsr6r <= #1 (lsr_mask || tx_fifo_write) ? 0 : lsr6r || (lsr6 && ~lsr6_d);
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< 	else lsr7r <= #1 lsr_mask ? 0 : lsr7 && ~lsr7_d;
---
> 	else lsr7r <= #1 lsr_mask ? 0 : lsr7r || (lsr7 && ~lsr7_d);
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< //assign thre_int = threi_clear ? 0 : ier[`UART_IE_THRE] && lsr[`UART_LS_TFE];
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> reg 	 rda_int_d;
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> 	if (wb_rst_i) rda_int_d <= #1 0;
> 	else rda_int_d <= #1 rda_int;
> 
> always  @(posedge clk or posedge wb_rst_i)
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> wire 	 rda_int_rise;
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> assign rda_int_rise    = rda_int & ~rda_int_d;
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> reg	rda_int_pnd;
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> 	if (wb_rst_i) rda_int_pnd <= #1 0; 
> 	else 
> 		rda_int_pnd <= #1 ((rf_count == {1'b0,trigger_level}) && fifo_read) ? 0 :  	// reset condition
> 							rda_int_rise ? 1 :						// latch condition
> 							rda_int_pnd && ier[`UART_IE_RDA];	// default operation: remove if masked
> 
> always  @(posedge clk or posedge wb_rst_i)
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< 		thre_int_pnd <= #1 thre_write || iir_read ? 0 : 
---
> 		thre_int_pnd <= #1 fifo_write || iir_read ? 0 : 
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< 					rda_int			? 1								:
---
> 					rda_int_pnd		? 1								:
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< 					thre_int_pnd	? !(thre_write & iir_read) :
---
> 					thre_int_pnd	? !(fifo_write & iir_read) :