64a65,67
> // Revision 1.29  2001/12/12 09:05:46  mohor
> // LSR status bit 0 was not cleared correctly in case of reseting the FCR (rx fifo).
> //
693,693c696,696
< 		thre_int_pnd <= #1 fifo_write || iir_read ? 0 : 
---
> 		thre_int_pnd <= #1 fifo_write || (iir_read & ~iir[`UART_II_IP] & iir[`UART_II_II] == `UART_II_THRE)? 0 :