64a65,80 > // Revision 1.38 2002/07/22 23:02:23 gorban > // Bug Fixes: > // * Possible loss of sync and bad reception of stop bit on slow baud rates fixed. > // Problem reported by Kenny.Tung. > // * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers. > // > // Improvements: > // * Made FIFO's as general inferrable memory where possible. > // So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx). > // This saves about 1/3 of the Slice count and reduces P&R and synthesis times. > // > // * Added optional baudrate output (baud_o). > // This is identical to BAUDOUT* signal on 16550 chip. > // It outputs 16xbit_clock_rate - the divided clock. > // It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use. > // 201,201c217,217 < //`include "uart_defines.v" --- > `include "uart_defines.v"